1. Field of the Invention
The invention generally relates to computer systems and in particular, to the implementation of a translation lookaside buffer ("TLB") within a computer system capable of performing speculative memory access operations.
2. Description of Related Art
Current state of the art microprocessors typically include one or more components for facilitating the processing of memory access operations. One such component is a data cache unit ("DCU") which stores a portion of data within a high speed memory. Typically, data from the most recently accessed external memory locations is stored within the DCU such that, if access to the data is required again, the data need not necessarily be retrieved from external memory. Another component commonly employed is a TLB which caches linear addresses and corresponding physical addresses for use in microprocessors wherein data is internally processed using only linear addresses. The TLB is used in connection with a page miss handler ("PMH") which performs a translation of a linear address to a physical address for those addresses not cached within the TLB. In use, the TLB is initially accessed to determine whether the TLB contains the physical address corresponding to a linear address identifying a desired memory location. If the linear address is found within the TLB, a "hit" is said to have occurred, and the physical address is merely loaded out of the TLB. If the linear and physical address are not cached within the TLB, then a TLB "miss" is said to have occurred and the PMH is accessed to perform a page table walk to determine the physical address corresponding to the desired linear address. Typically, a page table walk requires a considerable amount of execution time and may require two or more separate accesses to an external memory. It is primarily because the page table walk can be quite time consuming that the TLB is provided to allow for an immediate linear address translation for at least some of the linear addresses processed by the microprocessor.
During a TLB hit or during a page table walk in response to a TLB miss, a fault may be detected. Faults represent circumstances where normal processing of the loads or stores to the physical address cannot be properly processed. A wide variety of faults are commonly known. Examples include page and protection faults. In a page fault, the physical address identifies a page not presently held in memory which must be read from disk. A protection fault indicates that the physical address identifies a portion of memory for which the currently executing process does not have the privilege to access because, for example, the current process is a user program and the memory identified by the physical address corresponds to operating system ("OS") memory.
In conventional microprocessors, if a fault is detected, normal execution of the load or store causing the fault is suspended pending resolution of the fault. For microprocessors employing pipelined execution wherein portions of one or more loads or stores may be processed simultaneously, any loads or stores already in progress are aborted and flushed from the system. After the fault is resolved, the pipeline is reactivated and the additional loads or stores are re-executed. Microprocessors wherein processing of loads and stores is suspended or aborted upon the detection of a fault are said to have a "blocking" TLB, i.e., the TLB blocks processing of further instructions upon the detection of a fault.
Difficulties arise in the implementation of a blocking TLB for microprocessors capable of performing operations either out-of-order or speculatively. Out-of-order processing occurs when a microprocessor executes a micro-instruction, herein also referred to as an instruction, in advance of a later-generated instruction. In other words, actual execution of instructions need not be performed in the same order in which the instructions are generated or in which the instructions appear in a software program. Speculative processing occurs in a microprocessor capable of executing instructions which occur subsequent to a branch condition, such as an "If" statement, before the branch condition is actually resolved. In such systems, the microprocessor "guesses" as to which of two or more branches is likely to be taken. Such operations are termed "speculative" since it is not known whether the operations can actually be committed until the branch condition is resolved. If the branch prediction is found to be correct, then the speculatively executed instructions are committed to memory, i.e., the speculative instructions are "retired". If the branch prediction is found to be incorrect, then the speculatively executed instructions are squashed or flushed from the system.
As can be appreciated, the capability of performing operations speculatively can result in a great windfall in processing speed, since the microprocessor need not wait for a branch condition to be resolved prior to executing subsequent instructions. The advantages of performing operations out-of-order or speculatively is ideally exploited in microprocessors which are also capable of pipelined execution wherein two or more operations are performed simultaneously. General principles of out-of-order or speculative execution of instructions are described in "Superscalar Microprocessor Design" by Mike Johnson, Prentice-Hall, Inc. 1991.
Although speculative processing has considerable advantages over non-speculative processing, certain difficulties arise in handling faults within microprocessors capable of speculative execution. In particular, if a blocking TLB is employed, execution of instructions may be blocked as a result of a fault detected for a mispredicted speculative instruction. The blocking of subsequent instructions and the execution of fault handling routines would be unnecessary and wasteful for faults arising from instructions later determined to be mispredicted. Also, although fault handling problems have been described with reference to the TLB, similar problems may arise upon the detection of faults from other components of the microprocessor, such as the DCU.
The present invention is drawn, in part, to solving problems which arise in handling faults in microprocessors capable of speculative or out-of-order execution of memory, and other, instructions.